It is often useful to observe the internal signals of a circuit for purposes of debugging and/or verification. With respect to programmable logic device (PLD) types integrated circuit devices (ICs), a variety of techniques exist that allow a designer to observe the internal signals of a circuit design once instantiated within a PLD. One technique relies upon probes that are inserted into the physical implementation of the circuit within the PLD. Probes are implemented using the programmable logic elements of the PLD that are otherwise available for implementing the circuit design, also referred to as the design under test (DUT). The probes can be instantiated within the DUT at user-selected locations.
In some cases, each probe can be communicatively linked with an input/output (I/O) pin of the PLD via a physical route. The I/O pins that are coupled to the probes can be communicatively linked with a host computer executing analysis software. Accordingly, each probe requires an I/O pin in order to observe the signal collected by that probe. In other cases, a logic analyzer can be instantiated within the PLD to operate cooperatively with the DUT. Signals of interest collected by probes are routed to the “in-circuit” logic analyzer within the PLD. Samples can be sent from the PLD to a host computer executing suitable analysis software. As samples are usually sent through a dedicated interface, the number of I/O pins of the PLD that are reserved for probing, as compared to directly coupling probes to I/O pins, may be reduced.
When using probes, signals of interest must be identified prior to implementation of the circuit design within the PLD. The programmatic description of the circuit design must be modified to specify probes at desired locations, e.g., at signal paths of interest. After probes are inserted, the circuit design is synthesized, mapped, placed, routed, and converted into a bitstream. The bitstream can be loaded into the PLD to instantiate the DUT with any specified probes included therein.
During testing and/or verification, the particular signals that a designer may wish to observe can change. In other cases, the number of signals that a designer may wish to observe may be more than the number of signals that can be probed at any given time, whether a constraint of the in-circuit logic analyzer or a limitation of the number of I/O pins available on the PLD. Both situations are not uncommon given the complexity of modern circuit designs.
To insert new probes and/or remove existing probes, the programmatic description of the circuit design must be altered. Once modified, the circuit design can be re-synthesized, re-mapped, re-placed, re-routed, and converted to a bitstream. This process can require a significant amount of time, e.g., hours or possibly an entire day, making it difficult to quickly reconfigure probes during execution of the DUT.
Another technique of observing internal signals of a circuit design within a PLD is to read portions of configuration data directly form the PLD during execution of the DUT. PLDs provide a configuration read-back function that allows frames of configuration data to be output to a host computer system for analysis. This allows a developer to observe internal signals of a DUT at a specific execution time without the use of probes.
To read a frame of configuration data from the PLD, the clock of the PLD is stopped. A selected frame of configuration data can be read from the PLD. The frame indicates the entire state of the circuit, e.g., memory content, state of logic elements, and state or connectivity of routing resources, for those elements of the PLD that are configured by the selected frame. The state of a signal of interest, therefore, can be ascertained by determining the state of the component that drives or outputs the signal of interest.
While configuration read-back allows a designer to observe most of the internal signals of DUT at a specific time during execution, to obtain the current value of a signal the DUT clock must be stopped. After stopping the clock, the selected configuration frame can be read out to a host computer through an Internal Configuration Access Port (ICAP) or a Joint Test Action Group (JTAG) boundary scan interface. ICAP and/or JTAG interfaces, however, typically run at slower speeds than the PLD. For example, it often takes several clock cycles to read a single frame of configuration data from the PLD. If a designer wishes to continuously probe signals, the desired frames must be read-back on each clock cycle of the simulation, which can significantly slow down the speed of debugging and verification since the DUT clock must be continually stopped and restarted.